IC Packaging
Caliber Interconnects is one of the leading providers of IC package design services for various sectors such as the communication, computing, consumer & automotive industries. Our services include flip-chip, wire bond, stacked-die, System-in-Package (SiP), Package-on-Package (PoP), Package-in-Package (PiP), Chip-Scale-Package (CSP), Chiplet designs & QFN assembly services.
We at Caliber provide different types of IC packages and vertical space transformers (MLO/MLC/LTCC/hybrid-interconnection substrates) for ATE testing applications, high-speed digital package of ICs, mixed-signal ICs and RFIC products. Our engineers have a high degree of expertise in signal integrity and power integrity analysis with a strong capability to perform Simultaneous Switching Noise (SSN) SI/PI simulations and parasitic package extractions. Using the latest Ansys, we also perform system-level SI timing analysis and power integrity optimization. We coordinate with the assembly house and substrate foundry to achieve the right substrate at the first time and also make strict adherence to assembly specifications. Our process includes the validation of design for fab house DFM specification with our experienced CAM team.
- SIP4150SPB Allegro
- SIP226SPB APD SiP layout option
- More than 1250+ package designs successfully completed
- Layer count from 1-2-1 for Wirebond, 8-2-8 for flipchip up to 15-24-15 for MLO and 58 ceramic layers for MLC designs
- Low cost 4 layers laminates
- Multi layer ceramic designs
Lead Time 1 to 3 weeks from frozen netlist based on complexity
High speed design & Analysis services
- SiP designs & Chiplet designs
- Flipchip and Wirebond designs
- Stacked die packages
- Multi-Chip Module (MCM) designs
- Chip Scale Package designs
- LTCC & HTCC designs
- Specialized in design services for medical and defense sectors
- MLO/MLC/Coreless/Hybrid Substrate designs, Interposers for probe cards designs
Reliable services that make a difference
Chip-Scale-Package (CSP) & QFN Assembly Services
Stacked-die
Multi-layer package design
Multi - chip modules
Package-on-Package (PoP) & Package in Package (PiP)
Flipchip and Wirebond
Probe Cards
System in Packages
MLO/MLC substrate design
TOOLS EXPERTISE
- Cadence APD, PCB Editor and Cadence SIP
- Autocad for POD & Mechanical drawings
- CAM 350 and Genesis for validating gerbers
- Mentor Expedition up to 2.14
- In-house tools & skills
- Altium designer
Excellence in our specialized areas
- Mentor and Allegro package designer, Cadence Sigrity tools and Altium designer
- Flip-chip BGA, wire-bond BGA, Chiplet designs, Stacked die packages, CSP, PoP, PiP, MLO/MLC package for ATE hardware
- Early-stage SI & PI analysis and optimization
- SSN analysis based on SI/PI, co-design flow using SPICE netlist
- Power integrity and decoupling cap optimization
- Thermal and Mechanical Aspects of Package Design
- SiP design for various applications including cellular, Bluetooth, WLAN, GPS, camera, PDA and CMOS sensor
- IC/Package/Board co-design flow
- Package RLC extraction & package model generation for SI/PI analysis
- Thermal & mechanical design
