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Chip Solutions

DFT / DV

Design Verification

Physical Design Services

FPGA

Gate Level Simulations

JasperGold
Mixed signal SOC
Cost-effective service optimized for your design

Design Verification – DV

Our team of ASIC/FPGA verification experts specializing in the design of FPGA, can help you create comprehensive test plans and test benches to ensure the success of your project. With our extensive experience in power-aware and formal verification techniques for FPGA design, we have developed a comprehensive verification infrastructure, including stimulus generators, drivers, monitors, scoreboards, assertions, and constrained random coding.

Capabilities

Design verification (DV) at both the register-transfer level (RTL) and gate level, which includes unit delay and SDF-annotated simulations

Power-aware verification

Formal verification

Development of verification infrastructure, such as stimulus generators, drivers, monitors, scoreboards, assertions, and constrained random coding

Proficiency in languages such as Verilog, SystemVerilog, Specman, Vera, C++, C, and SystemC

Expertise in tools like ModelSim, NCSim, VCS, Debussy, MVSIM, MVRC, and JasperGold

Experience in verifying designs for multi-chip modules (MCM)

Our senior management team has over 12 years of experience in the DV field.


Our team of experts also has experience in verifying designs for multi-chip modules (MCM), in addition to proficiency in various languages and expertise in verification infrastructure and tools. Our senior management team's extensive experience in the DV field ensures that we deliver high-quality verification services that meet your project's specific needs.

Design For Test - DFT

In order to achieve optimal fault coverage, modern ASIC/SOC devices with millions of logic and functional blocks, including those packaged in Chip-Scale Packages, require a robust testing strategy. Our team of DFT consultants offers solutions to address the growing complexity of testing challenges in IC designs, ensuring that your Chip-Scale Package devices are thoroughly tested and meet the highest quality standards.

Capabilities

With our expertise in DFT (Design for Test) and DFD (Design for Debug) architecture and planning, we provide comprehensive solutions to meet your needs. Our team of experienced engineers, with an average of 15 years of experience, has worked with reputable clients such as AMD, Genesis, Teranitics, and PLX. We have successfully handled more than 50 designs, from initial architecture to final silicon bring-up, including high-speed processors and mixed-signal SOC products. Our services include TAP controller (BSCAN) insertion, analog DFT, DFD test bus planning, scan dump, RO/LBIST definition and specification, DFT mode STA, multiple clock and power domains, pattern debug and yield enhancement, RMA analysis, SCAN insertion and ATPG pattern generation, as well as MBIST with repair.

Physical Design
Services

We provide design and post-silicon test services to leading semiconductor companies, leveraging the expertise of our 50+ experienced design resources. Our state-of-the-art EDA design infrastructure and tailored foundry-specific processes ensure optimal performance results.

For over a decade, Caliber Interconnects has been delivering comprehensive layout services spanning from chip to package to PCB.

Team
Expertise

RTL synthesis and DFT, covering areas such as scan, ATPG, MBIST, and LBIST
Floor planning, place and route, IR drop analysis, and power optimization
High power and high frequency physical design capabilities
Flexibility in our working models, allowing us to take complete ownership of your physical design requirements
Experience working with deep sub-micron node processes
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