Chip Solutions

IC Package Design

Just Bond The Dies

IC Package Design

Caliber is one of the leading providers of IC package design services for various sectors such as the Communication, Computing, Consumer & Automotive industries. Our services include flip-chip, wire bond, stacked-die, System-in-package (SiP), Package-on-package (PoP), Package-in-Package (PiP), and Chip-Scale-Package (CSP).

We at Caliber provide different types of IC packages and vertical space transformers (MLO/MLC) for ATE testing applications, high-speed digital ICs, mixed-signal ICs and RFIC products. Our engineers have a high degree of expertise in signal integrity and power integrity analysis with a strong capability to perform Simultaneous Switching Noise (SSN) SI/PI simulations and parasitic package extractions. Using the latest Ansys, we also perform system-level SI timing analysis and power integrity optimization. We coordinate with the assembly house and substrate foundry to achieve the right substrate the first time and also make strict adherence to assembly specifications. Our process includes the validation of design for fab house DFM specification with our experienced CAM team. 

 Expertise In:

Cadence sigrity tools

The thermal and mechanical aspects of package design

Flip-chip, BGA, wire-bond BGA, chip-scale-package (CSP),Package on Package (PoP),

Package-in-Package (PiP) design, MLO/MLC package for ATE hardware

System-in-Package (SiP) design for applications such as cellular, bluetooth, WLAN, GPS, camera, PDA and CMOS sensor

Signal Integrity & Power Integrity analysis & optimization during early stage of package design

IC/Package/Board co - design flow

SSN analysis based on SI/PI, co - design flow using the SPICE netlist

Package RLC extraction & package model generation for SI/PI analysis

Power Integrity and decoupling cap optimization

Design tools – Mentor and Allegro package designer

Thermal & mechanical design

Leading Provider Of High Speed Design And Analysis Services For:

Probe cards

System in packages (SiP)

Multi-layer package designing and layouts

Multi chip modules (MCMs)

MLO/MLC substrate designs

Highly Skilled Design/Analysis And Layout Team

More than 800+ package designs successfully completed

Organic build up from 1-2-1 to 10-16-10 layers

Low cost 4 layers laminates

Multi layer ceramic designs

Cost-Effective And Timely Job Completion

Lead Time 1.5 to 3 weeks from frozen netlist based on complexity

Advanced Tools

SIP4150SPB - Allegro (R) package designer plus

SIP226SPB - APD SiP layout option