IC TEST ENGINEERING SERVICES

Test Applications   

• Test strategy and planning
• Prototype Testing
• Wafer Sorting/Final test (low/high volumes).
• Qualification and Characterization.
• Production releases.
• Cross Tester Platform conversion.
• IP Development.

Sustaining support

• Parallel/multisite test solution.
• Pattern compression.
• TTR/Yield improvement/RMA.

Services

• Cost optimized turnkey test engineering.
• Unified platform architecture development and JIRA systems.
• Test consulting.
• Postproduction and support.
• Tester Remote Access support.

Products Portfolio

• Digital.
• Analog.
• Mixed Signal.
• SOC/IOT

.

Test Engineering Infrastructure

SoC Tester

• Advantest V93K – Smart Scale
• Teradyne UFlex

• Advantest V93K
• Teradyne Eagle ETS
• Teradyne J750
• Vector Conversion Tools
• TSSI/VTRAN/Velocity

• Thermostream ATS-545-M-9

Overview:

Caliber Interconnect solutions Pvt Ltd has in depth experience in designing and developing validation boards for major semiconductor companies keen to evaluate their products in a quick and cost-effective way.

• More than 1000+ evaluation boards have been designed and delivered.
• Demonstrated expertise in successfully validating a multitude of ICs High Speed digital, RF, and/or Mixed Signal.
• Strong partnership with many leading EDA companies and has exclusive access to the latest tools and methodologies.
• Solid exposure on IC protocols including I2C, JTAG, MPI, etc,.
• A firm handle on firmware on different micro controller platforms including different ARM controllers, connectivity chip sets enabling to devise an easy to use, intuitive, robust firmware (and GUI) stack from a preliminary data sheet to showcase the capabilities of the Silicon.
• Leverages dexterity of engineers handling EDA design tools and IP driven process to design and develop boards which can be used from the day one - right at the first time on the schedule.
• In house simulation expertise to ensure the reliability of hardware and to analyze various SI/PI issues like reflection due to impedance mismatch, crosstalk, signal attenuation, and PDN noise which affects the interconnect performance.
• With assistance from our EMS partners, we speed up proto and production board requirements ahead of schedule.

• PCI Express, Gigabit Ethernet, USB, HDMI, SPI, I2C, CAN, DDR etc.

• I/O interfaces including USB, HDMI, SPI, I2C, Ethernet etc.
• CPU, GPU, VPU, DMAC

• Across PVT electrical validation.
• Power characterization,Validation.
• Bespoke test cases & standard benchmarks.

• Test case automation and regression.
• Board Bring-up and interface development.
• Full range of functional, performance and power validation.

• Measurement tools - CRO, LA, Spectrum Analyzer, Protocol Analyzer.
• Automation tools/environments - Labview, PYTHON, PERL.

• In ATE testing, test development time plays a crucial part influencing time to market. With the increasing complexity and technology of SOC chips, the development time becomes even more critical. This paper deals with the possible automation of test development and describes about its implementation to effectively cutting down test development time and manual efforts.
• TestGeni, an intelligent automation tool developed by Caliber Interconnect Solutions, generates a ready to load test flow from primary setup files. It reduces more than 60% of manual effort involved in Test preparation. This tool accepts different formats of primary setup files from Test Engineers and creates a standard format file for supporting all ATE test platforms (e.g., V93000 SM7 and SM8; IG XL uFlex). It auto validates input parameters given by Test Engineers and generates pin configuration files (including mapping channels, grouping pins and ports, etc) on its own and engenders loadable files of levels and time for DuT from the setup primary itself. Cross portability between Production testing, Characterization testing and Debug test flow has also been supported in this tool. By generating vectors with any memory size with zero manual error,  this tool goes a long way in reducing the manual effort in testing memory ICs.
• It uses Data Analytic, Data visualization techniques and fault detecting algorithms for automation. Also this tool engenders test coverage reports and allows  in test flow editing with lot of ease.