In ATE testing, test development time plays a crucial part influencing time to market. With the increasing complexity and technology of SOC chips, the development time becomes even more critical. This paper deals with the possible automation of test development and describes about its implementation to effectively cut down test development time and manual efforts
TestGeni, an intelligent automation tool developed by Caliber Interconnects Private Limited generates a ready to load test flow from primary setup files. It reduces more than 60% of manual effort involved in test preparation. This tool accepts different formats of primary setup files from test engineers and creates a standard format file for supporting all ATE test platforms (e.g., V93000 SM7 and SM8; IG XL uFlex). It auto validates input parameters given by test engineers and generates pin configuration files (including mapping channels, grouping pins and ports, etc.) on its own and engenders loadable files of levels and time for DuT from the setup primary itself. Cross portability between production testing, characterization testing and debug test flow has also been supported in this tool. By generating vectors with any memory size with zero manual error, this tool goes a long way in reducing the manual effort in testing memory ICs
It uses data analytic, data visualization techniques and fault detecting algorithms for automation. Also, this tool engenders test coverage reports and allows in test flow editing with a lot of ease
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