Signal Integrity (SI)
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Interconnects operating at high frequency and fast switching rates require thorough signal (SI) and power integrity (PI) analysis to get designs right the first time. Caliber strong knowledge of SI theory and expertise in simulation tools to analyze various issues like reflection due to impedance mismatch, crosstalk, signal attenuation and PDN noise. The analysis is carried out in the pre and post- layout

Pre-Layout Analysis

Interconnects operating at high frequency and fast switching rates require thorough signal (SI) and power integrity (PI) analysis to get designs right the first time. Caliber strong knowledge of SI theory and expertise in simulation tools to analyze various issues like reflection due to impedance mismatch, crosstalk, signal attenuation and PDN noise. The analysis is carried out in the pre and post- layout at both IC Package/substrate and board level.

Post Layout Analysis

Simulations of the routed board for potential issues like reflection, overshoot/undershoot, crosstalk, attenuation, EMI and PDN issues. A post layout report is prepared from simulation results along with suggestions for topology modification, termination schemes and layout modification to achieve optimal signal and power integrity

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High Speed Channel Modeling
  • Backplane, Add-in Card via breakout, connectors and cables
  • Using highly accurate ansys and sigrity 3D simulation tools, enable correct and optimized keeping channel loss within the spec
  • Long  SERDES channel with a high data rates require the use of different TX pre-emphasis, RX CTLE gain and DFE equalization tap factors so that the eye opening is solid at the receiver
  • These features are available in the ibis ami models
  • Experience in ami parameter variation and optimization for SERDES channel to keep the channel within the eye spec with the help of market leading simulation tools
PCB/Package

Signal Integrity Analysis

  • Reflection, ringing and overshoot/undershoot
  • Single ended and differential crosstalk analysis
  • Signal attenuation due to IR-Drop, skin-effect and dielectric loss
  • Channel analysis for serial communication – eye diagram analysis
  • IBIS/IBIS-AMI based system
  • Clock analysis (common & source synchronous)
  • DDR timing analysis
  • S - parameter analysis
    • Return & insertion loss, NEXT and FEXT analysis
    • Mixed mode analysis channel (common & differential)
  • Coupling analysis – Single and differential
  • Co - design (IC/package/board)
Power Integrity Analysis (PI)
  • SSN
  • IR - Drop
  • Power distribution network impedance profile
  • Transient noise estimation
  • Parasitic RLGC extraction
  • De-Coupling capacitors estimation and placement optimization
EMI/EMC Analysis
  • Net - wise radiated EMI
  • EMC analysis based on FCC, CISPR and VCCI requirement
Interfacing Technologies

Simulation capabilities & experience :

  • SDRAM, QDR, DDR2, DDR3 & DDR4 technology, eMMC
  • PCI, PCI-X, PCIe
  • MIPI, CSI, HDMI
  • FSB, Hub, Interface
  • USB, USB-OTG, HT, SATA, SAS
  • SERDES, XAUI, RocketIO, Aurora, Gigabit ethernet
  • SRIO, CPRIO
  • QSFP/SFP optical modules
  • Firefly connectors
  • 28Gbps channel using IBIS/AMI models
  • Up to 100GHz RF channels
Analysis Tools Expertise
  • Cadence Allegro PCB SI/PI
  • Cadence Allegro Package SI/PI along with Paksi 3D
  • Cadence Allegro SiP SI/PI along with Paksi 3D
  • Cadence Allegro SigXplorer
  • LTSpice
  • Ansys Electromagnetic 15.0
  • Cadence Sigrity Tool
  • Ansys SiWave
  • Ansys HFSS
Advanced Tools
  • SYS942   - Clarity IC package extraction suite
  • SIGR302 - Sigrity power SI II
  • SYS103   - Celcius power DC
We are a Product Engineering Company with a proven track record of offering Integrated product engineering solutions for major global players of diverse industries like Semiconductor, Avionics, Railways, Industrial, IOT (Internet of Things).